(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to a method of forming self-aligned, L-shaped sidewall spacers adjacent to polysilicon traces and transistor gates in the manufacture of integrated circuit devices.
(2) Description of the Prior Art
Sidewall spacers are used in the generation of the lightly doped drain (LDD) region in transistor structures. The move from 0.35 microns to 0.25 microns and below necessitates the use of silicon nitride and silicon dioxide. The migration to silicon nitride provides an improved margin for the pre-salicide clean process. As the physical geometry of the emerging technologies is getting smaller, the processing for pattern transfer and deposition becomes more challenging, especially the interlevel dielectric (ILD) gap fill process. Forming the silicon nitride spacer by a conventional dry etch process proves very challenging. The complexity of such an etch process results in too much variation in the width of the spacer. This variation is particularly sensitive to variations in the concentration of devices across the circuit.
FIG. 1 illustrates an integrated circuit device of the prior art. A partially completed LDD transistor is shown. A semiconductor substrate 10 is shown. Shallow trench isolations 14 (STI) are formed in the semiconductor to isolate the active device area. A transistor gate is shown comprised of a thin gate oxide 22 and a polysilicon gate electrode 26. In practice, this polysilicon gate electrode 26 may be comprised of multiple levels of polysilicon or may include other resistivity lowering layers. The lightly doped drains 18 are implanted after the formation of the transistor gate and are, therefore, self-aligned to the gate.
An oxide liner layer 30 is formed overlying the polysilicon gate electrode 26. This oxide liner layer improves the adhesion of the silicon nitride. The silicon nitride layer 34 is deposited overlying the oxide liner layer 30.
Referring now to FIG. 2, the silicon nitride layer 34 and the oxide liner layer 30 are anisotropically etched, as conventional in the art, to form sidewall spacers adjacent to the polysilicon gates. The conventional etching process produces spacers with curved profiles 38.
With the decreasing device size, there are two main problems with the silicon nitride spacers formed in this process. First, it is difficult to produce consistent, low variation spacer widths because of the etching process. Second, though the sidewalls are curved, the sidewall profiles are too sharp. As the distance between polysilicon gates is decreased, it becomes very difficult to fill the gap between adjacent gates without creating voids in the interlevel dielectric material.
Several prior art approaches disclose methods to form and fabricate sidewall spacers. U.S. Pat. No. 5,661,049 to Lur et al teaches a process to form sidewalls for transistors. Voids are formed in the sidewalls for stress relief. Polysilicon is used for a portion of the sidewalls. U.S. Pat. No. 5,013,675 to Shen et al discloses a process to form polysilicon sidewall spacers and to remove them using an etchant. Silicon dioxide is used as a gate liner underlying the polysilicon spacers. U.S. Pat. No. 5,899,722 to Huang teaches a process to form sidewall spacers of silicon nitride by anisotropically etching a silicon nitride layer. U.S. Pat. No. 5,498,555 to Lin discloses processes to form sidewall spacers of: oxide-polysilicon, oxide-polysilicon-oxide, oxide-nitride, and oxide-nitride-oxide. U.S. Pat. No. 5,891,788 to Fazan et al teaches a process to form local oxidation of silicon (LOCOS) isolations using polysilicon spacers around a masking material. Co-pending U.S. patent application Ser. No. 09/439,368 (CS-99-066) to P. Yelehanka et al, filed on Oct. 28, 1999, teaches a 2-step insitu etch to form L-shaped nitride spacers.
A principal object of the present invention is to provide an effective and very manufacturable method of fabricating silicon nitride sidewall spacers adjacent to polysilicon traces and polysilicon transistor gates in the manufacture of integrated circuits.
A further object of the present invention is to provide a method to fabricate silicon nitride sidewall spacers with L-shaped profiles that improve dielectric material gap fill.
Another further object of the present invention is to provide a method to fabricate L-shaped sidewall spacers with improved process control of the width of the spacers.
In accordance with the objects of this invention, a new method of forming silicon nitride sidewall spacers has been achieved. A semiconductor substrate is provided. An isolation region is provided overlying the semiconductor substrate. Polysilicon traces are provided overlying the insulator layer. A liner oxide layer is formed overlying the polysilicon traces and the insulator layer. A silicon nitride layer is formed overlying the liner oxide layer. A polysilicon or amorphous silicon layer is deposited overlying the silicon nitride layer. The polysilicon or amorphous silicon layer is completely oxidized to form a temporary silicon dioxide layer. The temporary silicon dioxide layer is rounded in the corners due to volume expansion during the oxidation step. The temporary silicon dioxide layer is anisotropically etched through to expose the horizontal surfaces of the silicon nitride layer while leaving the vertical sidewalls of the temporary silicon dioxide layer. The temporary silicon dioxide layer and the silicon nitride layer are anisotropically etched to remove all of the temporary silicon dioxide layer and to form silicon nitride sidewall spacers. The presence of the specially shaped temporary silicon dioxide layer causes the silicon nitride sidewall spacers to form an L-shaped profile. The integrated circuit device is completed.
Also in accordance with the objects of this invention, L-shaped silicon nitride sidewalls having an improved interlevel dielectric gap filling ability are described. A semiconductor substrate is provided. An insulator layer overlays the semiconductor substrate. Polysilicon traces overlay the insulator layer. A liner oxide layer overlays the polysilicon traces. Silicon nitride sidewall spacers, with an L-shaped profile, ring the perimeter of the polysilicon traces and overlay the insulator layer. An interlevel dielectric layer overlays the polysilicon traces, silicon nitride sidewall spacers, and the insulator layer and fills the spaces between the silicon nitride sidewall spacers to complete the device.